/**
 * @file    gt9881_timer.h
 * @author  Giantec-Semi ATE
 * @brief   CMSIS GT98xx Device Peripheral Access Layer Header File
 * @version 0.1
 * 
 * @copyright Copyright (c) 2021 Giantec-Semi
 * 
 */

#ifndef GT98XX_DEVICE_GT9881_TIMER_H_
#define GT98XX_DEVICE_GT9881_TIMER_H_

#ifdef __cplusplus
  extern "C" {
#endif /* __cplusplus */

#include "gt9881.h"

/**
 * @addtogroup Peripheral_Registers_Structures
 * @{
 */
/**
 * @struct TimerTypedef
 * @brief  Timer registers structure definition
 */
typedef struct tagTimerTypedef {
  __IO uint32_t LOAD;           ///< Load trigge
  __IO uint32_t LOAD_VALUE;     ///< Load value
  __IO uint32_t COUNT;          ///< Current value
  __IO uint32_t CAP1_VALUE;     ///< Captured value1
  __IO uint32_t CAP2_VALUE;     ///< Captured value2
  __IO uint32_t COMP_VALUE;     ///< Match value
  __IO uint32_t CONTROL;        ///< Control register
  __IO uint32_t IRQ_STA;        ///< Interrupt request status
  __IO uint32_t IRQ_RAW;        ///< Interrupt request raw status
  __IO uint32_t IRQ_EN;         ///< Interrupt request enable
} TimerTypedef;
/** @} Peripheral_Registers_Structures */

/**
 * @addtogroup Peripheral_Memory_Map
 * @{
 */
#define TIMER0_BASE             (PERIPH_BASE + 0xA000UL)    ///< Timer0 base address
#define TIMER1_BASE             (TIMER0_BASE + 0x40UL)      ///< Timer1 base address
#define TIMER2_BASE             (TIMER1_BASE + 0x40UL)      ///< Timer2 base address
#define TIMER3_BASE             (TIMER2_BASE + 0x40UL)      ///< Timer3 base address
/** @} Peripheral_Memory_Map */

/**
 * @addtogroup Peripheral_Declaration
 * @{
 */
#define TIMER0                  ((TimerTypedef*)TIMER0_BASE)    ///< Timer0 operator
#define TIMER1                  ((TimerTypedef*)TIMER1_BASE)    ///< Timer1 operator
#define TIMER2                  ((TimerTypedef*)TIMER2_BASE)    ///< Timer2 operator
#define TIMER3                  ((TimerTypedef*)TIMER3_BASE)    ///< Timer3 operator
/**
 * @def   TMR_IRQ_STA
 * @brief All timer's IRQ status for quick check
 * <pre>
 * @a 1'b0 : No event pending
 * @a 1'b1 : IRQ event pending
 * </pre>
 */
#define TMR_IRQ_STA             (*(__IO uint32_t *)(PERIPH_BASE + 0xA200UL))
/** @} Peripheral_Declaration */

/**
 * @defgroup TIMER_Bitmap Timer Bitmap 
 * @ingroup  Peripheral_Registers_Bits_Definition
 * @brief    Bitmap of Timer Registers
 * @{
 */

#define TMR_LOAD_Pos                    (0U)    ///< Position of TMR_LOAD
#define TMR_LOAD_Msk                    (0x1UL << TMR_LOAD_Pos)   ///< Bitmask of TMR_LOAD
/**
 * @def   TMR_LOAD
 * @brief Load @ref TMR_LOAD_VALUE into timer n and clear clock pre-scale counter
 * <pre>
 * @a 1b'0 : No action
 * @a 1b'1 : Load
 * </pre>
 */
#define TMR_LOAD                        TMR_LOAD_Msk

#define TMR_LOAD_VALUE_Pos              (0U)    ///< Position of TMR_LOAD_VALUE
#define TMR_LOAD_VALUE_Msk              (0xFFFFFFFFUL << TMR_LOAD_VALUE_Pos)    ///< Bitmask of TMR_LOAD_VALUE
/**
 * @def   TMR_LOAD_VALUE
 * @brief Value to be loaded into Timer N
 */
#define TMR_LOAD_VALUE                  TMR_LOAD_VALUE_Msk

#define TMR_COUNT_Pos                   (0U)    ///< Position of TMR_COUNT
#define TMR_COUNT_Msk                   (0xFFFFFFFFUL << TMR_COUNT_Pos)   ///< Bitmask of TMR_COUNT
/**
 * @def   TMR_COUNT
 * @brief Current value of Timer N counter
 */
#define TMR_COUNT                       TMR_LOAD_VALUE_Msk

#define TMR_CAP1_VALUE_Pos              (0U)    ///< Position of TMR_CAP1_VALUE
#define TMR_CAP1_VALUE_Msk              (0xFFFFFFFFUL << TMR_CAP1_VALUE_Pos)    ///< Bitmask of TMR_CAP1_VALUE
/**
 * @def   TMR_CAP1_VALUE
 * @brief Timer N counter value captured on external event trigger for single capture mode
 */
#define TMR_CAP1_VALUE                  TMR_CAP1_VALUE_Msk

#define TMR_CAP2_VALUE_Pos              (0U)    ///< Position of TMR_CAP2_VALUE
#define TMR_CAP2_VALUE_Msk              (0xFFFFFFFFUL << TMR_CAP2_VALUE_Pos)    ///< Bitmask of TMR_CAP2_VALUE
/**
 * @def   TMR_CAP2_VALUE
 * @brief Timer N counter value captured on external event trigger for second capture mode
 */
#define TMR_CAP2_VALUE                  TMR_CAP2_VALUE_Msk

#define TMR_COMP_VALUE_Pos              (0U)    ///< Position of TMR_COMP_VALUE
#define TMR_COMP_VALUE_Msk              (0xFFFFFFFFUL << TMR_COMP_VALUE_Pos)    ///< Bitmask of TMR_COMP_VALUE
/**
 * @def   TMR_COMP_VALUE
 * @brief Value to be compared with timer N counter
 */
#define TMR_COMP_VALUE                  TMR_COMP_VALUE_Msk

#define TMR_IRQ_STA_MAT_INT_STA_Pos     (0U)    ///< Position of TMR_IRQ_STA_MAT_INT_STA
#define TMR_IRQ_STA_MAT_INT_STA_Msk     (0x1UL << TMR_IRQ_STA_MAT_INT_STA_Pos)    ///< Bitmask of TMR_IRQ_STA_MAT_INT_STA
/**
 * @def   TMR_IRQ_STA_MAT_INT_STA
 * @brief Timer n's IRQ status for match
 * <pre>
 * Read
 * @a 1'b0 : No event pending
 * @a 1'b1 : IRQ event pending
 * Write
 * @a 1'b0 : No action
 * @a 1'b1 : Clear pending event, if any
 * </pre>
 */
#define TMR_IRQ_STA_MAT_INT_STA         TMR_IRQ_STA_MAT_INT_STA_Msk

#define TMR_IRQ_STA_OVF_INT_STA_Pos     (1U)    ///< Position of TMR_IRQ_STA_OVF_INT_STA
#define TMR_IRQ_STA_OVF_INT_STA_Msk     (0x1UL << TMR_IRQ_STA_OVF_INT_STA_Pos)    ///< Bitmask of TMR_STA_OVF_INT_STA
/**
 * @def   TMR_IRQ_STA_OVF_INT_STA
 * @brief Timer n's IRQ status for overflow
 * <pre>
 * Read
 * @a 1'b0 : No event pending
 * @a 1'b1 : IRQ event pending
 * Write
 * @a 1'b0 : No action
 * @a 1'b1 : Clear pending event, if any
 * </pre>
 */
#define TMR_IRQ_STA_OVF_INT_STA         TMR_IRQ_STA_OVF_INT_STA_Msk

#define TMR_IRQ_STA_CAP_INT_STA_Pos     (2U)    ///< Position of TMR_IRQ_STA_CAP_INT_STA
#define TMR_IRQ_STA_CAP_INT_STA_Msk     (0x1UL << TMR_IRQ_STA_CAP_INT_STA_Pos)    ///< Bitmask of TMR_IRQ_STA_CAP_INT_STA
/**
 * @def   TMR_IRQ_STA_CAP_INT_STA
 * @brief Timer n's IRQ status for capture
 * <pre>
 * Read
 * @a 1'b0 : No event pending
 * @a 1'b1 : IRQ event pending
 * Write
 * @a 1'b0 : No action
 * @a 1'b1 : Clear pending event, if any
 * </pre>
 */
#define TMR_IRQ_STA_CAP_INT_STA         TMR_IRQ_STA_CAP_INT_STA_Msk

#define TMR_IRQ_RAW_MAT_INT_RAW_Pos     (0U)    ///< Position of TMR_IRQ_RAW_MAT_INT_RAW
#define TMR_IRQ_RAW_MAT_INT_RAW_Msk     (0x1UL << TMR_IRQ_RAW_MAT_INT_RAW_Pos)    ///< Bitmask of TMR_IRQ_RAW_MAT_INT_RAW
/**
 * @def   TMR_IRQ_RAW_MAT_INT_RAW
 * @brief Timer n's IRQ status for match
 * <pre>
 * Read
 * @a 1'b0 : No event pending
 * @a 1'b1 : IRQ event pending
 * Write
 * @a 1'b0 : No action
 * @a 1'b1 : Clear pending event, if any
 * </pre>
 */
#define TMR_IRQ_RAW_MAT_INT_RAW         TMR_IRQ_RAW_MAT_INT_RAW_Msk

#define TMR_IRQ_RAW_OVF_INT_EN_Pos      (1U)    ///< Position of TMR_IRQ_RAW_OVF_INT_EN
#define TMR_IRQ_RAW_OVF_INT_EN_Msk      (0x1UL << TMR_IRQ_RAW_OVF_INT_EN_Pos)   ///< Bitmask of TMR_IRQ_RAW_OVF_INT_EN
/**
 * @def   TMR_IRQ_RAW_OVF_INT_EN
 * @brief Timer n's IRQ enable for overflow
 * <pre>
 * Read
 * @a 1'b0 : IRQ disabled
 * @a 1'b1 : IRQ enabled
 * Write
 * @a 1'b0 : IRQ disabled
 * @a 1'b1 : IRQ enabled
 * </pre>
 */
#define TMR_IRQ_RAW_OVF_INT_EN          TMR_IRQ_RAW_OVF_INT_EN_Msk

#define TMR_IRQ_RAW_CAP_INT_RAW_Pos     (2U)    ///< Position of TMR_IRQ_RAW_CAP_INT_RAW
#define TMR_IRQ_RAW_CAP_INT_RAW_Msk     (0x1UL << TMR_IRQ_RAW_CAP_INT_RAW_Pos)    ///< Bitmask of TMR_IRQ_RAW_CAP_INT_RAW
/**
 * @def   TMR_IRQ_RAW_CAP_INT_RAW
 * @brief Timer n's IRQ status for capture
 * <pre>
 * Read
 * @a 1'b0 : No event pending
 * @a 1'b1 : IRQ event pending
 * Write
 * @a 1'b0 : No action
 * @a 1'b1 : Clear pending event, if any
 * </pre>
 */
#define TMR_IRQ_RAW_CAP_INT_RAW         TMR_IRQ_RAW_CAP_INT_RAW_Msk

#define TMR_IRQ_EN_MAT_INT_EN_Pos       (0U)    ///< Position of TMR_IRQ_EN_MAT_INT_EN
#define TMR_IRQ_EN_MAT_INT_EN_Msk       (0x1UL << TMR_IRQ_EN_MAT_INT_EN_Pos)    ///< Bitmask of TMR_IRQ_EN_MAT_INT_EN
/**
 * @def   TMR_IRQ_EN_MAT_INT_EN
 * @brief Timer n's IRQ enable for overflow
 * <pre>
 * Read
 * @a 1'b0 : IRQ disabled
 * @a 1'b1 : IRQ enabled
 * Write
 * @a 1'b0 : IRQ disabled
 * @a 1'b1 : IRQ enabled
 * </pre>
 */
#define TMR_IRQ_EN_MAT_INT_EN           TMR_IRQ_EN_MAT_INT_EN_Msk

#define TMR_IRQ_EN_OVF_INT_EN_Pos       (1U)    ///< Position of TMR_IRQ_EN_OVF_INT_EN
#define TMR_IRQ_EN_OVF_INT_EN_Msk       (0x1UL << TMR_IRQ_EN_OVF_INT_EN_Pos)    ///< Bitmask of TMR_IRQ_EN_OVF_INT_EN
/**
 * @def   TMR_IRQ_EN_OVF_INT_EN
 * @brief Timer n's IRQ enable for match
 * <pre>
 * Read
 * @a 1'b0 : IRQ disabled
 * @a 1'b1 : IRQ enabled
 * Write
 * @a 1'b0 : IRQ disabled
 * @a 1'b1 : IRQ enabled
 * </pre>
 */
#define TMR_IRQ_EN_OVF_INT_EN           TMR_IRQ_EN_OVF_INT_EN_Msk

#define TMR_IRQ_EN_CAP_INT_EN_Pos       (2U)    ///< Position of TMR_IRQ_EN_CAP_INT_EN
#define TMR_IRQ_EN_CAP_INT_EN_Msk       (0x1UL << TMR_IRQ_EN_CAP_INT_EN_Pos)    ///< Bitmask of TMR_IRQ_EN_CAP_INT_EN
/**
 * @def   TMR_IRQ_EN_CAP_INT_EN
 * @brief Timer n's IRQ enable for match
 * <pre>
 * Read
 * @a 1'b0 : IRQ disabled
 * @a 1'b1 : IRQ enabled
 * Write
 * @a 1'b0 : IRQ disabled
 * @a 1'b1 : IRQ enabled
 * </pre>
 */
#define TMR_IRQ_EN_CAP_INT_EN           TMR_IRQ_EN_CAP_INT_EN_Msk

#define TMR_CONTROL_EN_Pos              (0U)    ///< Position of TMR_CONTROL_EN
#define TMR_CONTROL_EN_Msk              (0x1UL << TMR_CONTROL_EN_Pos)   ///< Bitmask of TMR_CONTROL_EN
/**
 * @def   TMR_CONTROL_EN
 * @brief Timer Enable
 * <pre>
 * @a 1'b0 : Timer disable
 * @a 1'b1 : Timer enable
 * </pre>
 */
#define TMR_CONTROL_EN                  TMR_CONTROL_EN_Msk

#define TMR_CONTROL_CAP_EVENT_Pos       (5U)    ///< Position of TMR_CONTROL_CAP_EVENT
#define TMR_CONTROL_CAP_EVENT_Msk       (0x3UL << TMR_CONTROL_CAP_EVENT_Pos)    ///< Bitmask of TMR_CONTROL_CAP_EVENT
/**
 * @def   TMR_CONTROL_CAP_EVENT
 * @brief Capture event setting
 * <pre>
 * @a 1'b0 : Capture mode disabled
 * @a 1'b1 : Capture on high-to-low transition
 * @a 1'b2 : Capture on low-to-high transition
 * @a 1'b3 : Capture on both transition edge
 * </pre>
 */
#define TMR_CONTROL_CAP_EVENT           TMR_CONTROL_CAP_EVENT_Msk

#define TMR_CONTROL_CAP_MODE_Pos        (7U)    ///< Position of TMR_CONTROL_CAP_MODE
#define TMR_CONTROL_CAP_MODE_Msk        (0x1UL << TMR_CONTROL_CAP_MODE_Pos)   ///< Bitmask of TMR_CONTROL_CAP_MODE
/**
 * @def   TMR_CONTROL_CAP_MODE
 * @brief Cap mode select
 * <pre>
 * @a 1'b0 : Single capture on the first valid event
 * @a 1'b1 : Capture on the second valid event
 * </pre>
 */
#define TMR_CONTROL_CAP_MODE            TMR_CONTROL_CAP_MODE_Msk

#define TMR_CONTROL_PULSE_TGL_Pos       (8U)    ///< Position of TMR_CONTROL_PULSE_TGL
#define TMR_CONTROL_PULSE_TGL_Msk       (0x1UL << TMR_CONTROL_PULSE_TGL_Pos)    ///< Bitmask of TMR_CONTROL_PULSE_TGL
/**
 * @def   TMR_CONTROL_PULSE_TGL
 * @brief Output mode on PWM output pin
 * <pre>
 * @a 1'b0 : Pulse
 * @a 1'b1 : Toggle
 * </pre>
 */
#define TMR_CONTROL_PULSE_TGL           TMR_CONTROL_PULSE_TGL_Msk

#define TMR_CONTROL_PWM_TRG_Pos         (9U)    ///< Position of TMR_CONTROL_PWM_TRG
#define TMR_CONTROL_PWM_TRG_Msk         (0x3UL << TMR_CONTROL_PWM_TRG_Pos)    ///< Bitmask of TMR_CONTROL_PWM_TRG
/**
 * @def   TMR_CONTROL_PWM_TRG
 * @brief Trigger output mode on PWM output pin
 * <pre>
 * @a 2'b00 : No trigger
 * @a 2'b01 : Trigger on overflow only
 * @a 2'b10 : Trigger on overflow and Match
 * @a 2'b11 : Trigger on Match only
 * </pre>
 */
#define TMR_CONTROL_PWM_TRG             TMR_CONTROL_PWM_TRG_Msk

#define TMR_CONTROL_MODE_Pos            (11U)   ///< Position of TMR_CONTROL_MODE
#define TMR_CONTROL_MODE_Msk            (0x1UL << TMR_CONTROL_MODE_Pos)   ///< Bitmask of TMR_CONTROL_MODE
/**
 * @def   TMR_CONTROL_MODE
 * @brief Timer mode
 * <pre>
 * @a 1'b0: Free-running mode
 * @a 1'b1: User define mode
 * </pre>
 */
#define TMR_CONTROL_MODE                TMR_CONTROL_MODE_Msk

#define TMR_CONTROL_AUTO_LD_Pos         (12U)   ///< Position of TMR_CONTROL_AUTO_LD
#define TMR_CONTROL_AUTO_LD_Msk         (0x1UL << TMR_CONTROL_AUTO_LD_Pos)    ///< Bitmask of TMR_CONTROL_AUTO_LD
/**
 * @def   TMR_CONTROL_AUTO_LD
 * @brief Timer counter mode
 * <pre>
 * @a 1'b0: One-shot
 * @a 1'b1: Auto-reload
 * </pre>
 */
#define TMR_CONTROL_AUTO_LD             TMR_CONTROL_AUTO_LD_Msk

#define TMR_CONTROL_COMP_EN_Pos         (13U)   ///< Position of TMR_CONTROL_COMP_EN
#define TMR_CONTROL_COMP_EN_Msk         (0x1UL << TMR_CONTROL_COMP_EN_Pos)    ///< Bitmask of TMR_CONTROL_COMP_EN
/**
 * @def   TMR_CONTROL_COMP_EN
 * @brief Compare mode enable
 * <pre>
 * @a 1'b0: Disable
 * @a 1'b1: Enable
 * </pre>
 */
#define TMR_CONTROL_COMP_EN             TMR_CONTROL_COMP_EN_Msk

#define TMR_CONTROL_UP_DWN_Pos          (14U)   ///< Position of TMR_CONTROL_UP_DWN
#define TMR_CONTROL_UP_DWN_Msk          (0x1UL << TMR_CONTROL_UP_DWN_Pos)   ///< Bitmask of TMR_CONTROL_UP_DWN
/**
 * @def   TMR_CONTROL_UP_DWN
 * @brief Timer counting mode
 * <pre>
 * @a 1'b0: Count Up intrerrupt occurs upon counting down to 0xFFFFFFFF
 * @a 1'b1: Count Down intrerrupt occurs upon counting down to 0
 * </pre>
 */
#define TMR_CONTROL_UP_DWN              TMR_CONTROL_UP_DWN_Msk

#define TMR_CONTROL_SRST_Pos            (15U)   ///< Position of TMR_CONTROL_SRST
#define TMR_CONTROL_SRST_Msk            (0x1UL << TMR_CONTROL_SRST_Pos)   ///< Bitmask of TMR_CONTROL_SRST
/**
 * @def   TMR_CONTROL_SRST
 * @brief Software reset to reset all functional circuit
 * <pre>
 * @a 1'b0 : Synchronous reset inactive
 * @a 1'b1 : Synchronous reset active
 * </pre>
 */
#define TMR_CONTROL_SRST                TMR_CONTROL_SRST_Msk

#define TMR_CONTROL_PWM_POL_Pos         (16U)   ///< Position of TMR_CONTROL_PWM_POL
#define TMR_CONTROL_PWM_POL_Msk         (0x1UL << TMR_CONTROL_PWM_POL_Pos)    ///< Bitmask of TMR_CONTROL_PWM_POL
/**
 * @def   TMR_CONTROL_PWM_POL
 * @brief Polarity selection of pulse on PWM port
 * <pre>
 * @a 1'b0 : Positive
 * @a 1'b1 : Negative
 * </pre>
 */
#define TMR_CONTROL_PWM_POL             TMR_CONTROL_PWM_POL_Msk

#define TMR_CONTROL_CLK_DIV_Pos         (17U)   ///< Position of TMR_CONTROL_CLK_DIV
#define TMR_CONTROL_CLK_DIV_Msk         (0x7FFUL << TMR_CONTROL_CLK_DIV_Pos)    ///< Bitmask of TMR_CONTROL_CLK_DIV
/**
 * @def   TMR_CONTROL_CLK_DIV
 * @brief Divisor for clock pre-scale
 * <pre>
 * Frequency divisor is (TMR_CLK_DIV+1)
 * </pre>
 */
#define TMR_CONTROL_CLK_DIV             TMR_CONTROL_CLK_DIV_Msk

/** @} TIMER_Bitmap */

/**
 * @addtogroup Exported_Macros
 * @{
 */

/**
 * @def   IS_TIMER_ALL_INSTANCE
 * @brief Check if INSTANCE is TIMER instance
 */
#define IS_TIMER_ALL_INSTANCE(INSTANCE)         (((INSTANCE) == TIMER0) || \
                                                 ((INSTANCE) == TIMER1) || \
                                                 ((INSTANCE) == TIMER2) || \
                                                 ((INSTANCE) == TIMER3))

/** @} Exported_Macros */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* GT98XX_DEVICE_GT9881_TIMER_H_ */
